This document relates in general to displays.
In some examples, a thin film transistor liquid crystal display (TFT-LCD) has a backlight module and a liquid crystal layer positioned between two glass substrates. In an active matrix liquid crystal display, transistors are fabricated on a glass substrate using semiconductor manufacturing processes. An amorphous silicon gate driver can be used to select a row of pixels into which data are written.
The amorphous silicon gate driver can have multiple shift registers. FIG. 1 is a circuit diagram of an example shift register 100, which includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor C. In this example, the transistors M1, M2, M3, and M4 are N-type MOSFETs. When an (n−1)th output signal OUTn−1 is at a high voltage level, the first transistor M1 is turned on to cause the third transistor M3 to be turned on, which causes the nth output signal OUTn to be at a high voltage level. The capacitor C pulls the voltage level at node P to be higher than the high voltage level to keep the third transistor M3 turned on.
When the (n+1)th output signal OUTn+1 is at the high voltage level, the second transistor M2 and the fourth transistor M4 are turned on, the voltage level at node P changes to a low voltage level VSS, and the nth output signal OUTn becomes equal to the low voltage level VSS. The third transistor M3 and the fourth transistor M4 are turned off for most of the frame period, so the voltage level of node O is floating for most of the frame period. Consequently, the voltage level of node O may be influenced by the voltage coupling to the data line so that the shift register 100 outputs the incorrect nth output signal OUTn to enable the thin film transistor to operate in an active region, such that the TFT-LCD displays an incorrect image frame.
FIG. 2 is a circuit diagram showing an example shift register 200, which includes seven N-type transistors M1 to M7, and a capacitor C. When the (n+1)th output signal OUTn+1 is at the high voltage level, the second transistor M2 is turned on such that the voltage level at node Q is at the low voltage level VSS, and the voltage level of node QB is at the high voltage level. The third transistor M3 is turned on to keep the voltage level at node Q at the low voltage level VSS, and the seventh transistor M7 is turned on to keep the voltage level at node O at the low voltage level VSS. As a result, the shift register 200 can output the correct nth output signal OUTn.
The third transistor M3 and the seventh transistor M7 are turned on for a long period of time, and are not turned off until the shift register 200 is triggered by the previous stage of the shift register to output the nth output signal OUTn. Because the third transistor M3 and the seventh transistor M7 are turned on for the long period of time, the threshold voltages of the third transistor M3 and the seventh transistor M7 may shift.
FIG. 3 shows current-voltage curves of a transistor that is turned on for about 6000 seconds. After being turned on for a long period of time, the third transistor M3 and the seventh transistor M7 have large threshold voltage shifts and may cause the shift register 200 to operate improperly.